In order to output a data from a semiconductor integrated circuit such as a semiconductor memory, it is necessary to establish a stable output potential by charging or discharging an output load at high speed. However, high speed charge/discharge of a load capacitor at the output side results in disturbance of a power supply voltage and ground potential because of rapid excessive load current. If a high speed operation is to be realized, the voltage disturbance becomes correspondingly large. This voltage disturbance is mainly determined by L.times.di/dt which is a product of a differential coefficient di/dt of a charge/discharge current and a parasitic inductance L of the path through which the charge/discharge current flows.
FIG. 1 is a circuit diagram of a semiconductor device of the background art. In FIG. 1, a circuit portion surrounded by a broken line represents a memory chip MCH. T1 represents a power supply voltage terminal for supplying a power supply potential to the memory chip, T2 represents a ground voltage terminal for supplying ground potential, T3 represents a data output terminal for outputting a data, and T4 represents an address input terminal for inputting an n-bit address (Ai). MCA represents a memory cell array, MC represents a memory cell, and DC represents an address decoder. D.C. power is supplied between the power supply voltage terminal T1 and ground voltage terminal T2 from a d.c. power source 111. The D.C. power source 111 is provided with a stabilizing capacitor 112 which absorbs noise on power supply lines. An n-bit address Ai is decoded by the address decoder DC to output a decoded signal. This decoded signal is used for selecting one memory cell MC within the memory cell array MCA. Data d of the selected MC is outputted as complementary data signals d and d. More specifically, an address signal Ai from the address input terminal T4 is supplied via an address input circuit (not shown) and used for reading a memory cell MC. The memory cell produces output drive signals d and d which are inputted to the gates of an "1" level output transistor 11 and "0" level output transistor 12, respectively. The interconnection between the "1" and "0" level output transistors 11 and 12 is connected to the data output terminal T3 of the memory chip MCH.
Between the positive terminal of the D.C. power source 111 and the power supply voltage terminal T1, there is a series circuit of an integrated circuit external parasitic inductor 16 and an integrated circuit external parasitic resistor 13. Between the negative terminal of the D.C. power source 11 and the ground voltage terminal T2, there is a series circuit of an integrated circuit external parasitic inductor 17 and an integrated circuit external parasitic resistor 14. Between the power supply voltage terminal T1 and the ground voltage terminal T2 within the memory chip MCH, there is an integrated circuit internal inter-terminal capacitor 19. At the output side of the data output terminal T3, there are an integrated circuit external parasitic inductor 18 and an integrated circuit external parasitic resistor 15 in series with the load capacitor 110.
With the circuit arrangement described above, data "0" is outputted from the data output terminal T3 in the following manner. Namely, the output drive data signal d is placed at a high level, to make the "0" level output transistor 12 conductive. Then, the electric charge of the load capacitor 110 is discharged to a path I via the data output terminal T3 so that the output level is established and a data "0" is outputted. In this case, noise is generated at the ground voltage terminal T2 because of the discharge current Id from the load capacitor 110 and the external parasitic resistors 14 and 15 are external parasitic inductors 17 and 18. Noise is also generated at the power supply voltage terminal T1 via the capacitor 19 within the memory chip MCH (coupling effect). Current also flows to a path II on the basis of a varying of potential at the terminal T1 at that time.
A series of such operations are represented by waveforms shown in FIG. 2 wherein the ordinate is voltage (volt) and the abscissa is time (t). FIG. 2 shows the changes of voltage levels at the power supply voltage terminal T1, ground voltage terminal T2, and data output terminal T3.
As seen from FIG. 2, as the level at the data output terminal T3 changes from the high level to the low level, large amounts of noise are generated at the power supply voltage terminal T1 and ground voltage terminal T2.
On the other hand, data "1" is outputted from the data output terminal T3 in the following manner. Namely, as shown in FIG. 3, the output drive data signal d is made high level to make the "1" level output transistor 11 conductive. Then, the load capacitor 110 is charged via the data output terminal T3 and a path III so that the output level is established and a data "1" is outputted. In this case, noise is generated at the power supply voltage terminal T1 because of the charge current Ic to the load capacitor 110 and the external parasitic resistors 13 and 15 and external parasitic inductors 16 and 18 of the path III. Noise is also generated at the ground voltage terminal T2 via the capacitor 19 within the memory chip MCH (coupling effect). Current also flows to a path IV on the basis of a varying of potential at the terminal T1 at that time.
A series of such operations are represented by waveforms shown in FIG. 4 wherein the ordinate is a voltage (volt) and the abscissa is a time (t). FIG. 4 shows the changes of voltage levels at the power supply voltage terminal T1, ground voltage terminal T2, and data output terminal T3.
As seen from FIG. 4, as the level at the data output terminal T3 changes from the low level to the high level, large amounts of noise are generated at the power supply voltage terminal T1 and ground voltage terminal T2.
In a semiconductor memory chip or the like having a plurality of data output terminals T3, noise generated at the power supply voltage terminal T1 and ground voltage terminal T2 become more conspicuous if data "0" or "1" is outputted from the data output terminals T3 at the same time. Noise at the power supply voltage terminal T1 and ground voltage terminal T2 cause corresponding noise to appear at the address input terminal T4. Such noise may cause an operation error or a delay in generating output data. If a charge/discharge current of the load capacitor is made small, noise can be reduced at the power supply voltage terminal T1 and ground voltage terminal T2. For this purpose, it becomes necessary to reduce the drive capacity of the "1" or "0" level output transistor 11, 12, i.e., to reduce the channel width of a MOS transistor. However, a limited drive capacity of an output transistor causes a delay of data access. Accordingly, the limited capacity of a transistor becomes a significant obstacle from the viewpoint of attaining high speed memory access. As described above, it is difficult for a conventional semiconductor device to sufficiently suppress the disturbance of power supply voltage and ground potential. Even if a load current is reduced, there occurs a new problem of redundancy of access time.